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L6561
POWER FACTOR CORRECTOR
VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION MICROPOWERSTART-UPCURRENT (50ATYP.) VERY LOW OPERATING SUPPLY CURRENT (4mA TYP.) INTERNAL START-UP TIMER CURRENT SENSE FILTER ON CHIP DISABLE FUNCTION 1% PRECISION (@ T j = 25C) INTERNAL REFERENCE VOLTAGE TRANSITION MODE OPERATION TOTEM POLE OUTPUT CURRENT: 400mA DIP8/SO8 PACKAGES DESCRIPTION L6561 is the improved version of the L6560 standard Power Factor Corrector. Fully compatible with the standard version, it has a superior performant multiplier making the device capable of working in wide input voltage range applications (from 85V to 265V) with an excellent THD. Furthermore the start up current has been reduced at few tens of A and a disable function has been implemented on the ZCD pin, guaranteeing lower current consumption in stand by mode. BLOCK DIAGRAM
COMP 2 INV 1 2.5V +
Minidip
SO8
ORDERING NUMBERS: L6561 (Minidip) L6561D (SO8)
Realised in mixed BCD technology, the chip gives the following benefits: - micro power start up current - 1% precision internal reference voltage (Tj = 25C) - Soft Output Over Voltage Protection - no need for external low pass filter onthe current sense - verylow operating quiescent current minimises power dissipation The totem pole output stage is capable of driving a Power MOS or IGBT with source and sink currents of +/- 400mA. The device is operating in transition mode and it is optimised for Electronic Lamp Ballast application, AC-DC adaptors and SMPS.
MULT 3 4 40K
CS
MULTIPLIER
VOLTAGE REGULATOR
OVER-VOLTAGE DETECTION
+
-
5pF
VCC
8
VCC INTERNAL SUPPLY 7V R1 + R2 VREF2 2.3V 1.8V + ZERO CURRENT DETECTOR STARTER UVLO R S DRIVER Q 7
20V
GD
DISABLE 6 GND 5 ZCD
D97IN547B
April 1999
1/11
L6561
ABSOLUTE MAXIMUM RATINGS
Symbol IVcc IGD INV, COMP MULT CS ZCD Ptot Tj Tstg Pin 8 7 1, 2, 3 4 5 ICC + IZ Output Totem Pole Peak Current (2s) Analog Inputs & Outputs Current Sense Input Zero Current Detector Power Dissipation @Tamb = 50 C Junction Temperature Operating Range Storage Temperature (Minidip) (SO8) Parameter Value 30 700 -0.3 to 7 -0.3 to 7 50 (source) -10 (sink) 1 0.65 -25 to 150 -55 to 150 Unit mA mA V V mA mA W C C
PIN CONNECTION
THERMAL DATA
Symbol Rth j-amb Parameter SO 8 150 MINIDIP 100 Unit C/W
Thermal Resistance Junction-ambient
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 Name INV COMP MULT CS ZCD GND GD VCC Function Inverting input of the error amplifier. A resistive divider is connected between the output regulated voltage and this point, to provide voltage feedback. Output of error amplifier. A feedback compensation network is placed between this pin and the INV pin. Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A voltage signal, proportional to the rectified mains, appears on this pin. Input to the comparator of the control loop. The current is sensed by a resistor and the resulting voltage is applied to this pin. Zero current detection input. If it is connected to GND, the device is disabled. Current return for driver and control circuits. Gate driver output. A push pull output stage is able to drive the Power MOS with peak current of 400mA (source and sink). Supply voltage of driver and control circuits.
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L6561
ELECTRICAL CHARACTERISTICS (VCC = 14.5V; T amb = -25C to 125C; unless otherwise specified) SUPPLY VOLTAGE SECTION
Symbol VCC VCC ON VCC OFF Hys Pin 8 8 8 8 Parameter Operating Range Turn-on Threshold Turn-off Threshold Hysteresis Test Condition after turn-on Min. 11 11 8.7 2.2 12 9.5 2.5 Typ. Max. 18 13 10.3 2.8 Unit V V V V
SUPPLY CURRENT SECTION
Symbol ISTART-U Iq ICC Iq VZ 8 Pin 8 8 Parameter Start-up Current Quiescent Current Operating Supply Current Quiescent Current Zener Voltage CL = 1nF @ 70KHz in OVP condition Vpin1 = 2.7V VPIN5 150mV, VCC > VCC off VPIN5 150mV, VCC < VCC off ICC = 25mA 20 18 Test Condition before turn-on (VCC =11V) Min. 20 Typ. 50 2.6 4 1.4 1.4 50 20 Max. 90 4 5.5 2.1 2.1 90 22 Unit A mA mA mA mA A V
ERROR AMPLIFIER SECTION
Symbol VINV Pin 1 Parameter Voltage Feedback Input Threshold Line Regulation IINV GV GB ICOMP VCOMP 2 2 1 Input Bias Current Voltage Gain Gain Bandwidth Source Current Sink Current Upper Clamp Voltage Lower Clamp Voltage VCOMP = 4V, VINV = 2.4V VCOMP = 4V, VINV = 2.6V ISOURCE = 0.5mA ISink = 0.5mA -2 2.5 Open loop 60 Test Condition Tamb = 25C 12V < VCC < 18V VCC = 12 to 18V Min. 2.465 2.44 2 -0.1 80 1 -4 4.5 5.8 2.25 -8 Typ. 2.5 Max. 2.535 2.56 5 -1 mV A dB MHz mA mA V V Unit V
MULTIPLIER SECTION
Symbol VMULT VCS Vmult K Pin 3 Parameter Linear Operating Voltage Output Max. Slope VMULT = from 0V to 0.5V VCOMP = Upper Clamp Voltage VMULT = 1V VCOMP = 4V Test Condition Min. 1.65 Typ. 1.9 Max. Unit V 0 to 3 0 to 3.5
Gain
0.45
0.6
0.75
1/V
CURRENT SENSE COMPARATOR
Symbol VCS ICS td (H-L) Pin 4 4 4 4 Parameter Current Sense Reference Clamp Input Bias Current Delay to Output Current Sense Offset Test Condition VMULT = 2.5V VCOMP = Upper Clamp Voltage VOS = 0 Min. 1.6 Typ. 1.7 -0.05 200 0 Max. 1.8 -1 450 15 Unit V A ns mV
3/11
L6561
ELECTRICAL CHARACTERISTICS (continued) ZERO CURRENT DETECTOR
Symbol VZCD Pin 5 Parameter Input Threshold Voltage Rising Edge Hysteresis VZCD VZCD VZCD IZCD IZCD IZCD VDIS IZCD 5 5 5 5 5 5 5 5 Upper Clamp Voltage Upper Clamp Voltage Lower Clamp Voltage Sink Bias Current Source Current Capability Sink Current Capability Disable threshold Restart Current After Disable VZCD < Vdis; VCC > VCCOFF (1) (1) IZCD = 20A IZCD = 3mA IZCD = -3mA 1V VZCD 4.5V -3 3 150 -100 200 -200 0.3 4.5 4.7 0.3 Test Condition Min. Typ. 2.1 0.5 5.1 5.2 0.65 2 -10 10 250 -300 0.7 5.9 6.1 1 Max. Unit V V V V V A mA mA mV A
OUTPUT SECTION
VGD 7 Dropout Voltage IGDsource = 200mA IGDsource = 20mA IGDsink = 200mA IGDsink = 20mA tr tf IGD off 7 7 7 Output Voltage Rise Time Output Voltage Fall Time IGD Sink Current CL = 1nF CL = 1nF VCC =3.5V VGD = 1V 5 40 40 10 1.2 0.7 2 1 1.5 0.3 100 100 V V V V ns ns mA A V s
OUTPUT OVERVOLTAGE SECTION
IOVP 2 OVP Triggering Current Static OVP Threshold 35 2.1 40 2.25 45 2.4
RESTART TIMER
tSTART Start Timer 70 150 400
(1) Parameter guaranteed by design, not tested in production.
OVER VOLTAGE PROTECTION OVP The output voltage is expected to be kept by the operation of the PFC circuit close to its nominal value. This is set by the ratio of the two external resistors R1 and R2 (see fig. 2), taking into consideration that the non inverting input of the error amplifier is biased inside the L6561 at 2.5V. In steady state conditions, the current through R1 and R2 is: IR1sc = Vout - 2.5 2.5V = IR2 = R1 R2
and, if the external compensation network is made only with a capacitor Ccomp, the current through Ccomp equals zero. When the output voltage increases abruptly the current through R1 becomes: IR1 =
4/11
Voutsc + VOUT - 2.5 = IR1sc + IR1 R1
Since the current through R2 does not change, IR1 must flow through the capacitor Ccomp and enter the error amplifier. This current is monitored inside the L6561 and when reaches about 37A the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 40A, the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 10A. However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condition keeping the external power switch turned off (see fig. 1). Finally, the overvoltage that triggers the OVP function is: Vout = R1 40A. Typical values for R1, R2 and C are shown in the application circuits. The overvoltage can be set independently from the average output voltage. The precision in setting the overvoltage threshold is 7% of
L6561
the overvoltage value (for instance V = 60V 4.2V). Disable function The zero current detector (ZCD) pin can be used Figure 1.
OVER VOLTAGE
for device disabling as well. By grounding the ZCD voltage the device is disabled reducing the supply current consumption at 1.4mA typical (@ 14.5V supply voltage). Releasing the ZCD pin the internal start-up timer will restart the device.
VOUT nominal
ISC
40A 10A
E/A OUTPUT 2.25V
DYNAMIC OVP
STATIC OVP
D97IN592A
Figure 2. Overvoltage Protection Circuit
Ccomp. +Vo R1 1 R2 + 2.5V 2.25V I +
E/A
I 2 X PWM
DRIVER
40A
D97IN591
5/11
L6561
Figure 3. Typical Application Circuit (80W, 110VAC)
D1 BYT03-400 C6 T R7 (*) 950K C3 680nF 68K 5 2 1 7 4
+
Vo=240V Po=80W
R3 (*) 240K BRIDGE + 4 x 1N4007 FUSE 4A/250V Vac (85V to 135V) NTC R10 10K
D3 1N4150 D2 1N5248B
R2 100
10nF R1
C1 1F 250V
R9 (*) 950K
8
R5 10
L6561
3 C2 22F 25V C7 10nF 6
MOS STP7NA40
C5 100F 315V
R6 (*) 0.31 1W
R8 10K 1%
D97IN549B
-
(*) R3 = 2 x 120K R6 = 0.619/2 R7 = 2 x 475K, 1% R9 = 2 x 475K
TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7) primary 90T of Litz wire 10 x 0.2mm secondary 11T of #27 AWG (0.15mm) gap 1.8mm for a total primary inductance of 0.7mH
Figure 4. Typical Application Circuit (120W, 220VAC)
D1 BYT13-600 C6 T R7 (*) 998K C3 1F 68K 5 2 1 7 4
+
Vo=400V Po=120W
R3 (*) 440K BRIDGE + 4 x 1N4007 FUSE 2A/250V Vac (175V to 265V) NTC R10 10K
D3 1N4150 D2 1N5248B
R2 100
10nF R1
C1 560nF 400V
R9 (*) 1.82M
8 3 C2 22F 25V C7 10nF
R5 10
L6561
6
MOS STP5NA50
C5 56F 450V
R6 (*) 0.41 1W
R8 6.34K 1%
D97IN550B
-
(*) R3 = 2 x 220K R6 = 0.82/2 R7 = 2 x 499K, 1% R9 = 2 x 909K
TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH
Figure 5. Wide-Range Application (80W)
D1 BYT13-600 C6 T R7 (*) 998K C3 1F 68K 5 2 1 7 4 R5 10 MOS STP8NA50
+
Vo=400V Po=80W
R3 (*) 240K BRIDGE + 4 x 1N4007 FUSE 4A/250V Vac (85V to 265V) NTC R10 10K
D3 1N4150 D2 1N5248B
R2 100
12nF R1
C1 1F 400V
R9 (*) 1.24M
8
L6561
3 C2 22F 25V C7 10nF 6
C5 47F 450V
R6 (*) 0.41 1W
R8 6.34K 1%
D97IN553B
-
(*) R3 = 2 x 120K R6 = 0.82/2 R7 = 2 x 499K, 1% R9 = 2 x 620K
TRANSFORMER T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8) primary 90T of Litz wire 10 x 0.2mm secondary 7T of #27 AWG (0.15mm) gap 1.25mm for a total primary inductance of 0.8mH
6/11
L6561
Figure 6. P.C. Board and Components Layout of the Figg. 3, 4 and 5 (1:1.25 scale) C O M P O N E N T S S I D E
S O L D E R S I D E
Figure 7. OVP Current Threshold vs. Temperature
D94IN047A
Figure 8. Undervoltage Lockout Threshold vs. Temperature
VCC-ON (V) 13
D94IN044A
IOVP (A)
41
12
40
11 VCC-OFF (V) 10 9
39
38 -50 -25 0 25 50 75 100 125 T (C)
-25
0
25
50 T (C)
75
100
125
7/11
L6561
Figure 9. Supply Current vs. Supply Voltage
ICC (mA) 10 5 1 0.5 0.1 0.05 0.01 0.005 0 0 5 10 15 20 VCC(V) C L = 1nF f = 70KHz TA = 25C
2.46 -50 0 50 100 T (C) 2.48 2.50
D97IN548A
Figure 10. Voltage Feedback Input Threshold vs. Temperature
VREF (V)
D94IN048A
Figure 11. Output Saturation Voltage vs. Sink Current
VPIN7 (V) VCC = 14.5V 2.0
D94IN046
Figure 12. Output Saturation Voltage vs. Source Current
VPIN7 (V) VCC = 14.5V
VCC -0.5
D94IN053
SINK
1.5
VCC -1.0
1.0
VCC -1.5
0.5
VCC -2.0
SOURCE 0 0 100 200 300 400 IGD (mA) 0 0 100 200 300 400 IGD (mA)
Figure 13. Multiplier Characteristics Family
VCS(pin4) (V) upper voltage
clamp
D97IN555A
VCOMP(pin2) (V)
3.5
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0
5.0
4.5
4.0 3.2
3.0
2.8 2.6
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VMULT(pin3) (V)
8/11
L6561
DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 0.51 1.15 0.356 0.204
mm TYP. 3.32 0.020 1.65 0.55 0.304 10.92 9.75 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.313 0.045 0.014 0.008 MAX. MIN.
inch TYP. 0.131 MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0.260 0.200 0.150 0.060
Minidip
9/11
L6561
DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1
mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN.
inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
10/11
L6561
.Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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